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M29KW032E
32 Mbit (2Mb x16, Uniform Block) 3V Supply LightFlashTM Memory
PRODUCT PREVIEW
FEATURES SUMMARY s SUPPLY VOLTAGE - VCC = 2.7V to 3.6V for Read - VPP = 11.4V to 12.6V for Program and Erase
s s
Figure 1. Packages
ACCESS TIME: 90, 110ns PROGRAMMING TIME - 9s per Word typical - Multiple Word Programming Option (4s typical Chip Program) TSOP48 (N) 12 x 20mm
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ERASE TIME - 21s typical factory Chip Erase UNIFORM BLOCKS - 16 blocks of 2 Mbits
s
FBGA
s
PROGRAM/ERASE CONTROLLER - Embedded Word Program algorithms 10,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE - Manufacturer Code: 0020h - Device Code : 88ACh TFBGA48 (ZA) 6 x 9mm
s
s
July 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
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TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 4. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Vss Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Word Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Program Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 11 Table 7. Multiple Word Program Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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Figure 5. Multiple Word Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VPP Status Bit (DQ4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Multiple Word Program Bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 10. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 12. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 13. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 11. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 14. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 15. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13. Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 16. Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 24 Table 17. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 24 Figure 15. TFBGA48 6x9mm - 8x6 ball array, 0.80 mm pitch, Bottom View Package Outline . . . . 25 Table 18. TFBGA48 6x9mm - 8x6 ball array, 0.80 mm pitch, Package Mechanical Data. . . . . . . . 25 Figure 16. TFBGA48 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 26 Figure 17. TFBGA48 Daisy Chain - PCB Connections (Top view through package) . . . . . . . . . . . 27 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 20. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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SUMMARY DESCRIPTION The M29KW032E LightFlashTM is a 32 Mbit (2Mb x16) non-volatile memory that can be read, erased and reprogrammed. Read operations can be performed using a single low voltage (2.7 to 3.6V) supply. Program and Erase operations require an additional VPP (11.4 to 12.6) power supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into 16 uniform blocks that can be erased independently so it is possible to preserve valid data while old data is erased (see Figures 2, Block Addresses). Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller (P/E.C.) simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents.
The M29KW032E LightFlashTM features a new command, Multiple Word Program, used to program large streams of data. It greatly reduces the total programming time when a large number of Words are written to the memory at any one time. Using this command the entire memory can be programmed in 2s, compared to 9s using the standard Word Program. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in TSOP48 (12 x 20mm) and TFBGA48 (6 x 9mm, 0.8mm pitch) packages. The memory is supplied with all the bits erased (set to '1').
Figure 2. Logic Diagram
VCC VPP
Table 1. Signal Names
A0-A20 DQ0-DQ15 E Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Reset Ready/Busy Output Supply Voltage read Supply Voltage program erase Ground Not Connected Internally
21 A0-A20 W E G M29KW032E
16 DQ0-DQ15
G W RP RB
RB RP
VCC VPP VSS
VSS
AI04370
NC
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Figure 3. TFBGA Connections (Top view through package)
1
2
3
4
5
6
A
A3
A7
RB
W
A9
A13
B
A4
A17
VPP
RP
A8
A12
C
A2
A6
A18
NC
A10
A14
D
A1
A5
A20
A19
A11
A15
E
A0
DQ0
DQ2
DQ5
DQ7
A16
F
E
DQ8
DQ10
DQ12
DQ14
NC
G
G
DQ9
DQ11
VCC
DQ13
DQ15
H
VSS
DQ1
DQ3
DQ4
DQ6
VSS
AI04372
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Figure 4. TSOP Connections Table 2. Block Addresses
Block Number 16 Address Range 1E0000h-1FFFFFh 1C0000h-1DFFFFh 1A0000h-1BFFFFh 180000h-19FFFFh 160000h-17FFFFh 140000h-15FFFFh 120000h-13FFFFh 100000h-11FFFFh 0E0000h-0FFFFFh 0C0000h-0DFFFFh 0A0000h-0BFFFFh 080000h-09FFFFh 060000h-07FFFFh 040000h-05FFFFh 020000h-03FFFFh 000000h-01FFFFh
A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 W RP NC VPP RB A18 A17 A7 A6 A5 A4 A3 A2 A1
1
48
A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
12 37 M29KW032E 13 36
24
25
AI04374
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SIGNAL DESCRIPTIONS See Figure 2, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A20). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ8-DQ15). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V IH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface. Reset (RP). The Reset pin can be used to apply a Hardware Reset to the memory. A Hardware Reset is achieved by holding Reset Low, V IL, for at least tPLPX. After Reset goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or t RHEL, whichever occurs last. See the Ready/Busy Output section, Table 16 and Figure 13, Reset AC Characteristics for more details. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode and Auto Select mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until
Ready/Busy becomes high-impedance. See Table 16 and Figure 13, Reset AC Characteristics. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. VCC Supply Voltage. The VCC Supply Voltage supplies the power for Read operations. The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1F capacitor should be connected between the V CC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC3. V PP Program Supply Voltage. VPP is both a power supply and Write Protect pin. The two functions are selected by the voltage range applied to the pin. The Supply Voltage VCC must be applied before the Program Supply Voltage VPP. If VPP is in the range 11.4V to 12.6V it acts as a power supply pin for program and erase operations. VPP must be stable until the Program/Erase algorithm is completed. If VPP is kept in a low voltage range (0V to 3.6V) VPP is seen as a Write Protect pin. In this case a voltage lower than VHH gives an absolute protection against program or erase, while VPP in the range of V HH enables these functions (see Table 12, DC Characteristics for the relevant values). Note that VPP must not be left floating or unconnected as the device may become unreliable. Vss Ground. The VSS Ground is the reference for all voltage measurements.
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BUS OPERATIONS There are six standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby, Automatic Standby and Electronic Signature. See Tables 3, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 10, Read Mode AC Waveforms, and Table 13, Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 11 and 12, Write AC Waveforms, and Tables 14 and 15, Write AC Table 3. Bus Operations
Operation Bus Read Bus Write Output Disable Standby Read Manufacturer Code Read Device Code
Note: 1. 2. 3. 4.
Characteristics, for details of the timing requirements. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V IH. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC 0.2V. For the Standby current level see Table 12, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes. Automatic Standby. If CMOS levels (VCC 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 3, Bus Operations.
E VIL VIL X VIH VIL VIL
G VIL VIH VIH X VIL VIL
W VIH VIL VIH X VIH VIH
VPP XX(4) VHH(3) X X XX XX
Address Inputs A0-A20 Cell Address Command Address X X A0 = VIL, A1 = VIL, Others VIL or VIH A0 = VIH, A1 = VIL, Others VIL or VIH
Data Inputs/Outputs DQ15-DQ0 Data Output Data Input Hi-Z Hi-Z 0020h 88ACh
X = VIL or VIH. XX = VIL , VIH or VHH Not necessary for Auto Select or Read/Reset commands. When reading the Status Register during Program or Erase operations, V PP must be kept at VHH.
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COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. Refer to Tables 4 and 5, for a summary of the commands. Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset Command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. Once the program or erase operation has started the Read/Reset command is no longer accepted. The Read/Reset command is executed regardless of the value of VPP (VIL, VIH or VHH). Auto Select Command. The Auto Select command is used to read the Manufacturer Code and the Device Code. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until a Read/Reset command is issued, all other commands are ignored. The Auto Select command is executed regardless of the value of VPP (VIL, VIH or VHH). From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V IL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. Word Program Command. The Word Program command can be used to program a Word to the memory array. V PP must be set to V HH during Word Program. If VPP is set to either VIL or VIH the command will be ignored, the data will remain unchanged and the device will revert to Read/Reset mode. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read operations during the program operation will output
the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at '0' back to '1'. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. Multiple Word Program Command The Multiple Word Program command can be used to program large streams of data. It greatly reduces the total programming time when a large number of Words are written to the memory at any one time. V PP must be set to VHH during Multiple Word Program. If VPP is set to either VIL or VIH the command will be ignored, the data will remain unchanged and the device will revert to Read/Reset mode. It has four phases: the Setup Phase to initiate the command, the Program Phase to program the data to the memory, the Verify Phase to check that the data has been correctly programmed and reprogram if necessary and the Exit Phase. Setup Phase. The Multiple Word Program command requires three Bus Write operations to initiate the command (refer to Table 5, Multiple Word Program Command and Figure 5, Multiple Word Program Flowchart). The Status Register Toggle bit (DQ6) should be checked to verify that the operation has started and the Multiple Word Program bit (DQ0) checked to verify that the P/E.C. is ready for the first Word. Program Phase. The Program Phase requires n+1 cycles, where n is the number of Words, to execute the programming phase (refer to Table 5, Multiple Word Program Command and Figure 5, Multiple Word Program Flowchart). Three successive steps are required to issue and execute the Program Phase of the command. 1. The fourth Bus Write operation of the command latches the Start Address and the first Word to be programmed. The Status Register Multiple Word Program bit (DQ0) should be read to check that the P/E.C. is ready for the next Word. 2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address can remain the Start Address, be incremented or be any address in the same block, as the device automatically increments the address with each sucssesive Bus Write
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M29KW032E
cycle. If the command is used to program in more than one block then the address must remain in the starting block as any address that is not in the same block as the Start Address terminates the Program operation. The Status Register Multiple Word Program bit (DQ0) must be read between each Bus Write cycle to check that the P/E.C. is ready for the next Word. 3. Finally, after all Words have been programmed, write one Bus Write operation to any address outside the block containing the Start Address, to terminate the programming phase. The memory is now set to enter the Verify Phase. Verify Phase. The Verify Phase is similar to the Program Phase in that all Words must be resent to the memory for them to be checked against the programmed data. If the check fails the P/E.C will try to reprogram the correct data. The P/E.C will remain busy until the correct data has been successfully programmed. The Verify Phase is mandatory. If the Verify Phase is not executed the programmed data cannot be guaranteed. Three successive steps are required to execute the Verify Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word, to be verified. The Status Register Multiple Word Program bit (DQ0) should be read to check that the P/E.C. is ready for the next Word. 2. Each subsequent Word to be verified is latched with a new Bus Write operation. If any address that is not in the same block as the Start Address is given, the Verify operation terminates. The Status Register Multiple Word Program (DQ0) must be read to check that the P/E.C. is ready for the next Word. 3. Finally, after all Words have been verified, write one Bus Write operation to any address outside the block containing the Start Address, to terminate the Verify Phase. Exit Phase . Read the Status Register to verify that DQ6 has stopped toggling. If the Verify Phase is successfully completed the memory returns to the Read mode. If the P/E.C. fails to reprogram a given location, the Verify Phase will terminate and Error bit DQ5 will be set in the Status Register. If the error is due to a V PP failure DQ4 will also be set. If the operation fails a Read/Reset command must be issued to return the device to Read mode. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. Note that the Multiple Word Program command cannot change a bit set at '0' back to '1'. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. Block Erase Command. The Block Erase command can be used to erase a block. It sets all of the bits in the block to '1'. All previous data in the block is lost. VPP must be set to V HH during Block Erase. If VPP is set to either V IL or V IH the command will be ignored, the data will remain unchanged and the device will revert to Read/Reset mode. Six Bus Write operations are required to select the block . The Block Erase operation starts the Program/Erase Controller after the last Bus Write operation. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation. During the Block Erase operation the memory will ignore all commands. Typical block erase times are given in Table 6. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Chip Erase Command. The Chip Erase command can be used to erase the entire memory. It sets all of the bits in the memory to '1'. All previous data in the memory is lost. VPP must be set to V HH during Chip Erase. If VPP is set to either V IL or V IH the command will be ignored, the data will remain unchanged and the device will revert to Read/Reset mode. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 6. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.
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Table 4. Standard Commands
Command Length Bus Write Operations 1st Add X 555 555 555 555 555 Data F0 AA AA AA AA AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 X 555 555 555 555 F0 90 A0 80 80 PA 555 555 PD AA AA 2AA 2AA 55 55 BA 555 30 10 2nd Add Data Add 3rd Data Add 4th Data Add 5th Data Add 6th Data
1 Read/Reset 3 Auto Select Word Program Block Erase Chip Erase 3 4 6+ 6
Note: X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ15 are Don't Care.
Table 5. Multiple Word Program Command
Length Bus Write Operations 1st Add 555 PA1 Data AA PD1 2nd Add 2AA PA1 Data 55 PD2 3rd Add 555 PA1 Data 20 PD3 4th Add PA1 PA1 Data PD1 PD4 5th Add PA1 PA1 Data PD2 PD5 Final -1 Add PA1 PA1 Data PAn PAn Final Add NOT PA1 NOT PA1 Data X X Phase
Program Verify
3+n +1 n+1
Note: A Bus Read must be done between each Write cycle where the data is programmed or verified, to Read the Status Register and check that the memory is ready to accept the next data. NOT PA1 is any address that is not in the same block as PA1. X Don't Care, n = number of Words to be programmed.
Table 6. Program, Erase Times and Program, Erase Endurance Cycles
Parameter Chip Erase Block Erase (128 KWords) Program (Word) Chip Program (Multiple Word) Chip Program (Word by Word) Program/Erase Cycles (per Block)
Note: 1. TA = 25C, VPP = 12V.
Min
Typ (1) 21 1.5 9 4 18
Typical after 10k W/E Cycles (1) 25
Max 120 6 250 35 35
Unit s s s s s cycles
10,000
Table 7. Multiple Word Program Timings
Symbol tMWP-SETUP tMWP-PROG tMWP-TRAN tMWP-END MWP Setup time MWP Program Time MWP Program to Verify transition MWP Verify to End transition 2 9 10 2 Parameter Min Typ Max 500 250 20 3 Unit ns s s s
Note: 1. MWP = Multiple Word Program.
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Figure 5. Multiple Word Program Flowchart
Setup Phase Start Write AAh Address 555h Read Status Register Verify Phase
(tMWP-TRAN(1))
Write 55h Address 2AAh DQ0 = 0? YES Write 20h Address 555h Write Data1 (PD1) Start Address (PA1) NO
Read Status Register NO Setup time exceeded? YES NO DQ6 toggling? YES
Read Status Register NO DQ0 = 0? YES Write Data 2 (PD2) Address in Start Block NO Word program time exceeded? YES
(tMWP-SETUP(1))
NO
(tMWP-PROG(1))
EXIT (setup failed)
DQ0 = 0? YES
Program Phase
Write Data1(PD1) Start Address (PA1)
Read Status Register NO
Read Status Register
DQ0 = 0? YES
NO
Word program time exceeded? YES
(tMWP-PROG(1))
DQ0 = 0? YES
NO Write Data n (PDn) Address in Start Block
Write Data 2 (PD2) Address in Start Block
Read Status Register NO
Read Status Register
NO DQ0 = 0? YES
Word program time exceeded? YES
(tMWP-PROG(1))
Read Status Register
Exit Phase
DQ0 = 0? YES
NO Write XX Any Address NOT in Start Block
Write Data n (PDn) Address in Start Block
Read Status Register
YES
DQ5 = 1 DQ4 = 0?
NO
Read Status Register DQ6 toggling? DQ0 = 0? YES Write XX Any Address NOT in Start Block NO NO YES
Fail error
Fail, VPP error
(tMWP-END(1))
Write F0h Address XX
Exit (read mode)
AI05554c
Note: 1. Refer to Table 7, Multiple Word Program Timings, for the values.
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STATUS REGISTER Bus Read operations from any address always read the Status Register during Program and Erase operations. The bits in the Status Register are summarized in Table 8, Status Register Bits. Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation. The Data Polling Bit is output on DQ7 when the Status Register is read. During a Word Program operation the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Word Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. The Data Polling Bit is not available during a Multiple Word Program operation. During Erase operations the Data Polling Bit outputs '0', the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. Figure 6, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased. Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. Figure 7, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit. Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to '1' when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to '0' back to '1' and attempting to do so will set DQ5 to `1'. A Bus Read operation to that address will show the bit is still `0'. One of the Erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. VPP Status Bit (DQ4). The VPP Status Bit can be used to identify if any Program or Erase operation has failed due to a VPP error. If VPP falls below V HH during any Program or Erase operation, the operation aborts and DQ4 is set to `1'. If VPP remains at VHH throughout the Program or Erase operation, the operation completes and DQ4 is set to `0'. Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to '1'. The Erase Timer Bit is output on DQ3 when the Status Register is read. Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Block and Chip Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations to any address. Once the operation completes the memory returns to Read mode. If an Erase operation fails and the Error Bit is set, the Alternative Toggle Bit will continue to toggle with successive Bus Read operations to any address. The Alternative Toggle Bit does not change if the addressed block has erased correctly. Multiple Word Program Bit (DQ0). The Multiple Word Program Bit can be used to indicate whether the Program/Erase Controller is active or inactive during Multiple Word Program. When the Program/Erase Controller has written one Word and is ready to accept the next Word, the bit is set to `0'. Status Register Bit DQ1 is reserved.
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Table 8. Status Register Bits
Operation Word Program Word Program Error Block/ Chip Erase Erase Error Condition Any Address VPP = VHH VPP < VHH Any Address VPP = VHH VPP < VHH P/E.C. active Multiple Word Program P/E.C. inactive, waiting for next Word VPP = VHH VPP < VHH DQ7 DQ7 DQ7 DQ7 0 0 0 - - - - DQ6 Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle DQ5 0 1 1 0 1 1 0 0 1 1 DQ4 - 0 1 - 0 1 - - 0 1 DQ3 - - - 1 1 1 - - - - DQ2 - - - Toggle(2) Toggle(2) Toggle(2) - - - - DQ0 - - - - - - 1 0 1 1 RB 0 0 0 0 0 0 0 1 0 0
Multiple Word Program Error
Note: 1. Unspecified data bits should be ignored. 2. DQ2 toggles on any address during Block or Chip Erase and after an Erase error.
Figure 6. Data Polling Flowchart
Figure 7. Data Toggle Flowchart
START READ DQ6
START
READ DQ5 & DQ7 at VALID ADDRESS
READ DQ5 & DQ6
DQ7 = DATA NO NO YES
DQ6 = TOGGLE YES
NO
DQ5 =1
NO
YES READ DQ7 at VALID ADDRESS
DQ5 =1 YES READ DQ6 TWICE
DQ7 = DATA NO FAIL
YES
DQ6 = TOGGLE
PASS
NO
YES FAIL PASS
AI01370B
AI03598
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MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at Table 9. Absolute Maximum Ratings
Symbol TBIAS TSTG VIO VCC VPP Temperature Under Bias Storage Temperature Input or Output Voltage (1,2) Read Supply Voltage Program/Erase Supply Voltage Parameter Min -50 -65 -0.6 -0.6 -0.6 Max 125 150 VCC +0.6 4 13.5 Unit C C V V V
these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Minimum voltage may undershoot to -2V for less than 20ns during transitions. 2. Maximum voltage may overshoot to V CC +2V for less than 20ns during transitions. 3. Maximum voltage may overshoot to 14.0V for less than 20ns during transitions. VPP must not remain at VHH for more than a total of 80hrs.
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DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement
Conditions summarized in Table 10, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 10. Operating and AC Measurement Conditions
M29KW032E Parameter Min VCC Read Supply Voltage VPP Program/Erase Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 0 to VCC VCC/2 2.7 11.4 0 30 10 0 to VCC VCC/2 90 Max 3.6 12.6 70 Min 2.7 11.4 0 30 10 110 Max 3.6 12.6 70 V V C pF ns V V Unit
Figure 8. AC Measurement I/O Waveform
Figure 9. AC Measurement Load Circuit
VCC VCC VCC/2 0V
AI05565
VCC
25k DEVICE UNDER TEST 25k
0.1F
CL
CL includes JIG capacitance
AI05566
Table 11. Device Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: Sampled only, not 100% tested.
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Table 12. DC Characteristics
Symbol ILI ILO ICC1 ICC2 ICC3 VIL VIH VOL VOH VHH IHH1 IHH2 VLKO Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Standby) Supply Current (Program/Erase) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP Program/Erase Voltage VPP Current (Read/Standby) VPP Current (Program/Erase) Program/Erase Lockout Supply Voltage VPP = VHH P/E.C. Active 1.8 IOL = 1.8mA IOH = -100A VCC -0.4 11.4 12.6 100 10 2.3 Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, G = VIH, f = 6MHz E = VCC 0.2V, RP = VCC 0.2V P/E.C. active -0.5 0.7VCC Min Max 1 1 10 100 20 0.8 VCC +0.3 0.45 Unit
A A
mA
A
mA V V V V V
A
mA V
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Figure 10. Read AC Waveforms
tAVAV A0-A20 tAVQV E tELQV tELQX G tGLQX tGLQV DQ0-DQ15 tGHQX tGHQZ VALID tEHQZ tEHQX VALID tAXQX
AI05567
Table 13. Read AC Characteristics
M29KW032E Symbol Alt Parameter Test Condition 90 tAVAV tAVQV tELQX (1) tELQV tGLQX (1) tGLQV tEHQZ (1) tGHQZ (1) tEHQX tGHQX tAXQX tRC tACC tLZ tCE tOLZ tOE tHZ tDF tOH Address Valid to Next Address Valid Address Valid to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Chip Enable, Output Enable or Address Transition to Output Transition E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL E = VIL Min Max Min Max Min Max Max Max Min 90 90 0 90 0 35 30 30 0 110 110 110 0 110 0 35 30 30 0 ns ns ns ns ns ns ns ns ns Unit
Note: 1. Sampled only, not 100% tested.
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Figure 11. Write AC Waveforms, Write Enable Controlled
tAVAV A0-A20 VALID tWLAX tAVWL E tELWL G tGHWL W tWHWL tDVWH DQ0-DQ15 VALID tWHDX tWLWH tWHGL tWHEH
VCC tVCHEL VPP tVPHEL RB tWHRL
AI05568
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Table 14. Write AC Characteristics, Write Enable Controlled
M29KW032E Symbol tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL Alt tWC tCS tWP tDS tDH tCH tWPH tAS tAH Parameter 90 Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low Read mode Read SR Toggle bits Read mode tWHGL tOEH Write Enable High to Output Enable Low Read SR Toggle bits in Multiple Word Program Read SR Toggle bits other operations tWHRL (1) tVCHEL tVPHEL(2) tBUSY Program/Erase Valid to RB Low tVCS tVCS VCC High to Chip Enable Low VPP High to Chip Enable Low Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Min Min 90 0 35 35 0 0 30 0 45 0 10 0 20 30 35 50 500 110 110 0 35 35 0 0 30 0 45 0 10 0 20 30 35 50 500 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns Unit
Note: 1. Sampled only, not 100% tested. 2. Not required in Auto Select or Read/Reset command sequences.
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Figure 12. Write AC Waveforms, Chip Enable Controlled
tAVAV A0-A20 VALID tELAX tAVEL W tWLEL G tGHEL E tEHEL tDVEH DQ0-DQ15 VALID tEHDX tELEH tEHGL tEHWH
VCC tVCHWL VPP tVPHWL RB tEHRL
AI05569
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Table 15. Write AC Characteristics, Chip Enable Controlled
M29KW032E Symbol tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL Alt tWC tWS tCP tDS tDH tWH tCPH tAS tAH Parameter 90 Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Read mode Low Read SR Toggle bits Read mode tEHGL tOEH Chip Enable High to Output Enable Low Read SR Toggle bits in Multiple Word Program Read SR Toggle bits other operations tEHRL (1) tVCHWL tVPHWL(2) tBUSY tVCS tVCS Program/Erase Valid to RB Low VCC High to Write Enable Low VPP High to Write Enable Low Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Min Min 90 0 35 35 0 0 30 0 45 0 10 0 20 30 35 50 500 110 110 0 35 35 0 0 30 0 45 0 10 0 20 30 35 50 500 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns Unit
Note: 1. Sampled only, not 100% tested. 2. Not required in Auto Select or Read/Reset command sequences.
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Figure 13. Reset AC Waveforms
W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL RP tPLPX
tPLYH
AI05570
Table 16. Reset AC Characteristics
M29KW032E Symbol tPHWL (1) tPHEL tPHGL
(1)
Alt
Parameter 90 RP High to Write Enable Low, Chip Enable Low, Output Enable Low 110
Unit
tRH
Min
50
50
ns
tRHWL (1) tRHEL (1) tRHGL
(1)
tRB
RB High to Write Enable Low, Chip Enable Low, Output Enable Low RP Pulse Width RP Low to Read Mode
Min
0
0
ns
tPLPX tPLYH (1)
tRP tREADY
Min Max
500 10
500 10
ns s
Note: 1. Sampled only, not 100% tested.
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PACKAGE MECHANICAL Figure 14. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
Note: Drawing is not to scale.
A1
L
Table 17. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C D D1 E e L N CP 0.50 0.05 0.95 0.17 0.10 19.80 18.30 11.90 - 0.50 0 48 0.10 Min Max 1.20 0.15 1.05 0.27 0.21 20.20 18.50 12.10 - 0.70 5 0.0197 0.0020 0.0374 0.0067 0.0039 0.7795 0.7205 0.4685 - 0.0197 0 48 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.7953 0.7283 0.4764 - 0.0276 5 inches
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Figure 15. TFBGA48 6x9mm - 8x6 ball array, 0.80 mm pitch, Bottom View Package Outline
D FD FE SD D1
SE BALL "A1" E E1 ddd
e e A A1 b A2
BGA-Z00
Note: Drawing is not to scale.
Table 18. TFBGA48 6x9mm - 8x6 ball array, 0.80 mm pitch, Package Mechanical Data
millimeters Symbol A A1 A2 b D D1 ddd E e E1 FD FE SD SE 9.000 0.800 5.600 1.000 1.700 0.400 0.400 8.900 - - - - - - 0.400 6.000 4.000 0.350 5.900 - 0.200 1.000 0.450 6.100 - 0.100 9.100 - - - - - - 0.3543 0.0315 0.2205 0.0394 0.0669 0.0157 0.0157 0.3504 - - - - - - 0.0157 0.2362 0.1575 0.0138 0.2323 - Typ Min Max 1.200 0.0079 0.0394 0.0177 0.2402 - 0.0039 0.3583 - - - - - - Typ inches Min Max 0.0472
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Figure 16. TFBGA48 Daisy Chain - Package Connections (Top view through package)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
AI05552b
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Figure 17. TFBGA48 Daisy Chain - PCB Connections (Top view through package)
END POINT START POINT 1 2 3 4 5 6
A
B
C
D
E
F
G
H
AI05553b
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PART NUMBERING Table 19. Ordering Information Scheme
Example: Device Type M29K = LightFlashTM Operating Voltage W = VCC = 2.7 to 3.6V Device Function 032E = 32 Mbit (x16) Speed 90 = 90 ns 110 = 110 ns Package N = TSOP48: 12 x 20 mm ZA = TFBGA48: 6 x 9mm - 0.80mm pitch Temperature Range 1 = 0 to 70 C Option T = Tape & Reel Packing
M29KW032E
90
N
1
T
Table 20. Daisy Chain Ordering Scheme
Example: Device Type M29K Daisy Chain DCL3-32 = Daisy Chain Level 3 for 32 Mbit parts Option T = Tape & Reel Packing M29K DCL3-32 T
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M29KW032E
REVISION HISTORY Table 21. Document Revision History
Date 09-Oct-2001 Version -01 First Issue LFBGA changed to TFBGA package. Write AC Characteristics tWLWH, tDVWH, tWLAX, tGHWL, tWHGL, tELEH, tDVEH, tELAX, tGHEL and tEHGL modified. Typical Chip Program and Erase times modified, Multiple Word Program description and flowchart clarified, Alternative Toggle Bit DQ2 description clarified, Status Register Bits Table modified. Document classed as Product Preview. Figure 7 modified. Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot. (revision version 03 becomes 3.0). Figure 5, Multiple Word Program Flowchart, modified; Table 7, Multiple Word Program Timings, added. Revision Details
07-May-2002
-02
12-Jul-2002
-03
23-Jul-2002
3.1
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M29KW032E
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics LightFlash is a trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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